• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:

    公开号:SU812197A3
    申请号:SU731963374
    申请日:1973-09-24
    公开日:1981-03-07
    发明作者:Шлихте Макс
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    SRI. They will go to another sequence of station clock bits.
    FIG. 1 shows a structural electrical circuit for the implementation of an even-scale method for relatively large propagation times. FIG. 2 shows a characteristic of a phase monomer (control characteristic); FIG. 3 shows a structural electrical circuit for the implementation of the proposed method with a short propagation time.
    The implementation scheme of the proposed method, -containing, for example, in a central telephone exchange of a multichannel communication system with time division multiplexing with code-pulse modulation, covering other. Kind of central telephone exchanges, has a station oscillator / clock frequency that is synchronized with principle phase averaging due to other generators of these central telephone exchanges through multichannel lines with a temporary seal of the channels coming from these central telephone exchanges .
    From the multichannel lines that are temporarily sealed to the circuit, which serve to transmit communication signals, linear bit cycles generated by oscillators provided in the other central telephone exchanges named and respectively executed are brought through inertial synchronization units 2 directly to the linear individual phase signals. discriminators 3, made in the form of triggers. In addition, the output of the station generator is connected to their counting inputs.
    The average output of each tilting stage corresponds to the phase difference between the linear binary signals and the stationary binary signals. The output signals from the phase discriminators 3 are fed through the summing circuit 4 on the resistors to the input of the low-pass filter 5. The output of the low-pass filter 5 forms a control signal regulating the frequency of the station oscillator.
    The phase discriminators 3 are directly loaded with the corresponding pulse sequence of linear binary signals and the sequence of pulses of station binary signals.
    The control characteristic in this implementation method is as shown in FIG. 2 by a flat line, where A / is the propagation time; AA is the expected range of propagation time fluctuations; QI - generator frequency at idle; yo is the upper and Qu are the lower frequencies of the generator, limiting the area of control of the station clock generator, p is the duration of the time interval per bit (the pulse repetition period of the sequence of pulses).
    As can be seen from FIG. 1, a pulse repetition period p of a sequence of pulses applied to a phase comparator is significantly less than the expected range of propagation time fluctuations.
    In the circuit depicted in FIG. 3, comprising a clock, as in the circuit of FIG. 1, separate lilter blot clocks through inertial synchronization blocks 2 are applied to phase discriminators 3 on triggers, output
    the signal of which is fed to the summing circuit 4 on the resistors, and from the output of the summing value 4 via a low-pass filter 5 to the station clock generator receives a control signal for frequency control.
    In contrast to the scheme according to FIG. 1 now the input belonging to both branches of the phase discriminators 3 is connected by control lines A, B, passing
    stationed binary signals shifted by 180 ° through a switch that switches to another control line B, respectively, A, respectively, with a synphasis between the binary signal appearing, and, respectively, on control line A, respectively, B and the binary signal of the corresponding multichannel lines with a temporary seal channels. For this both
    the control lines are connected, by circumstances, through the elements AND 6 and 7, connected to the element OR 8, with the corresponding inputs of the phase discriminator 3, each time the other two
    The inputs of elements b and 7 are connected to both outputs of the complementary element 9, so that depending on the operating state of the auxiliary element 9 can transmit the element 6 and 7 and 7. To the input of the auxiliary element 9 relative to both branches of the phase discriminator leads element AND 10, which is connected to its input with the output of the corresponding element OR vSj and its
    another input is connected to the output of the corresponding inertial synchronization unit 2. With this circuit, the frequency control characteristic shown in FIG. 2 two sawtooth-shaped curves.
    Any time the boundaries of the control area are reached, i.e. when the operating point in the control process reaches the end of the trailing edge of the saw-tooth curve, the auxiliary element 9 of the corresponding phase discriminator 5 is tilted from its previous working state to another working state, which leads to that working point
    权利要求:
    Claims (3)
    [1]
    is shifted from the end of the regulating characteristic to its middle, which corresponds to the characteristic shown in fig. 2 by the dashed line. In this way, undesirable repeated jumps of the operating point in the vicinity of the front of the saw-tooth curve, as well as in the operating point, which is subject to jitter due to the displacement of the jump-like places, are reliably eliminated by means of artificially introduced hysteresis. It should be noted that the adjustment characteristic shown in FIG. 2 by a power line, on its own, without the additional measures provided by the diagram of FIG. 3, has a natural hysteresis, sufficient for relatively long propagation times, in order to eliminate unwanted spikes in the regulation. Claim 1. Method of mutual synchronization of station clock frequency generators in network nodes with temporary compression, in particular with its pulse-code modulation, consisting in forming pulse sequences corresponding to the line clock. time-compressed, a sequence of pulses corresponding to the station clock, compare the clock frequency phases of the generated sequences and isolate, by averaging, the control signal of the station clock frequency generator, characterized in that, in order to avoid fluctuations in the clock frequency of the station clock , form a sequence of pulses with a period of pulses less than the oscillation of the propagation time of the corresponding line with the time lapse smoldering.
    [2]
    2. A method according to claim 1, characterized in that the pulse sequences are formed with a period equal to the period of the bits of the clock sequence of pulses of the corresponding line with a temporary compression equal to the period of the bits of the clock sequence of pulses of the station clock frequency generator.
    [3]
    3. The method according to claim 2, characterized in that the bit sequences of the station clock pulses are formed in the initial phase and shifted by 180 °, and when the phases are equal, the station clock pulse bit sequence and the line clock bit bits transition to another bit sequence clock pulses station. The source of information taken into account in the examination: 1. “The Bell System Technical Journal, volume XLV, December, 1966, No. 10, p. 1689-1744 (prototype).
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    引用文献:
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    GB1081012A|1964-11-18|1967-08-31|Ferranti Ltd|Improvements relating to frequency stabilising systems|
    US3504125A|1967-02-10|1970-03-31|Bell Telephone Labor Inc|Network synchronization in a time division switching system|
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    JPS4943809B1|1968-10-25|1974-11-25|IT1148884B|1980-07-09|1986-12-03|Sits Soc It Telecom Siemens|MULTIFREQUENCY TYPE SIGNALING CONTROL UNIT, OF PARTICULAR APPLICATION IN NUMERIC TYPE TRANSIT TELEPHONE UNITS|
    IT8121477D0|1981-04-30|1981-04-30|Italtel Spa|CIRCUITABLE PROVISION SUITABLE TO ALIGN A PLURALITY OF COHERENT PCM BANDS ARRIVING THEREOF, WHICH REACH A COMMUNICATION NODE.|
    EP0128554B1|1983-06-10|1988-03-30|Tocom, Inc.|Master/slave converter system|
    SE466474B|1990-07-10|1992-02-17|Ericsson Telefon Ab L M|CLEARING CIRCUIT FOR JITTER REDUCTION IN DIGITAL MULTIPLEX SYSTEM|
    US5228138A|1991-01-23|1993-07-13|Massachusetts Institute Of Technology|Synchronization of hardware oscillators in a mesh-connected parallel processor|
    KR0174596B1|1995-05-10|1999-04-01|김광호|Clock Receive Circuit for Network Synchronous Control of Switching System|
    FR2952197B1|2009-10-29|2012-08-31|Commissariat Energie Atomique|DEVICE FOR GENERATING CLOCK SIGNALS WITH ASYMMETRIC COMPARISON OF PHASE ERRORS|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE19722247666|DE2247666C2|1972-09-28|1972-09-28|Circuit arrangement for the mutual synchronization of the exchange clock oscillators provided in the exchanges of a PCM time division multiplex telecommunications network|
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